This invention relates generally to designing electrical circuits, and more particularly to providing systems and methods for swapping circuits in an engineering change metal-only (ECO) process.
The use of gate array cells is a technology used to place large numbers of logic circuits on single or integrated chips. Each gate array cell includes rows of transistors, and multiple gate array cells may be arranged on the surface of the chip. One or more gate array cells may be grouped together in a “gate array book” to form a logic device, i.e., “logic gate”, such as AND, NAND, OR or NOR gates. Each gate array book is provided to perform a specific logic function in an integrated circuit.
Circuit ECO processes are provided to fix or modify prior integrated circuit, i.e. “chip”, designs, and are generally implemented with the use of gate array filler cells, particularly late in the development cycle. These approaches seek to minimize the risk involved with changing circuits in the chip. Traditionally, in non-critical paths, devices with a higher gate threshold voltage (Vt), such as Complementary metal-oxide-semiconductor (CMOS) devices, are used to reduce the power dissipated, both in active and in non-active devices.
In typical designs, the Vt levels for gate array filler cells match the standard cells/circuit books used in the chip. However, situations can arise in circuit design where there are design changes, particularly changes that occur late in the design process. Such changes include design re-maps, introduction of new timing constraints to existing logic, and additional margin needs introduced to the design to minimize risk on logic paths.
Current technologies for swapping circuits focus heavily on swapping of existing logic gates in timing closure processes. Other standard solutions in place to address ECO swapping issues include redesigning circuits physically or logically to meet new or future restrictions, and remapping a design to new technology. All of these approaches can significantly impact the schedule of a design project and/or have significant cost implications to integrated circuit generation process, including front-end-of-line (FEOL) and back-end-of-line (BEOL) ECOs, and BEOL metal-only ECOs.
It would be desirable/advantageous to be able to provide a method and device to alter fully functional and fully-developed circuits by providing the best possible filler cell to meet functional and frequency requirements, without introducing significant delay or impacting a design process.